This invention relates generally to semiconductor packaging and in particular to packaging of semiconductor circuits into chip size packages by a method compatible with wafer processing.
The newest designs and concepts in microelectronics assembly and packaging are aiming for a package with a planar area not substantially greater than the silicon chip itself, or at most 20% larger area. This concept is known as Chip-Scale Package (CSP) and is finding particular favor with those electronics industries where the product size is continually shrinking such as cellular communications, pagers, hard disk drivers, laptop computers and medical instrumentation. Most CSP approaches are based on flip-chip assembly with solder bumps or solder balls on the exterior of the package, to interface with system boards.
A typical flip-chip process calls for solder-compatible contact pads on the circuit surface of the chip, and the deposition of solder bumps or balls thereon. The semiconductor wafers have to be separated into chips before flip-chip attachment to the board. Existing solder bump processes incorporate solder through metal masks, electroplated solder or screen printing a mound of solder paste onto each metallic contact. Typically the solder bumps are reflowed in a chain type furnace. Alternatively, solder balls may be placed on the chip pads and reflowed in a similar chain type furnace.
The chip-to-be-flipped may then be attached to a second interconnection surface such as an interposer, or alternatively, coupled directly to a printed circuit board (PCB). Attaching the flip-chip to the next interconnect is carried out by aligning the solder bumps or balls on the chip to contact pads on the second level interconnection and then performing a second solder reflow operation. During the reflow, the bumps or balls liquify and make a bond to the next interconnect level which has pads or traces to receive the solder. Following the solder reflow step, flip-chips often use a polymeric underfill between the chip and the interposer or PCB to alleviate mechanical stress caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the interposer, if any, and the PCB. Many reliability problems occur due to the stress placed on the solder bumps or balls when the integrated circuit is cycled from hot to cool during operation. The interposers and underfills of the prior art are used to reduce or eliminate the mechanical stress generated by thermal cycling on the solder bumps or balls.
When another set of solder balls on the opposite side of the interposer is employed to complete the bonding process to a PCB, this second may also be aligned and reflowed for attachment by the end user. When the chip is attached to the board as described, the final consumption of board area is usually not much larger the the area of the chip (about 20% larger). Consequently, this family of products is classified as xe2x80x9cchip-scale packagesxe2x80x9d.
Problems exist with conventional process equipment and flow for chip-scale packages using flip-chip technology. First, a typical solder bumping process is very equipment intensive, resulting in a large capital cost. Evaporation, plating and screening are environmentally unfriendly in that they make use of excess of solder, often containing lead. Both processing and clean-up costs are high in these operations.
Second, the manufacturing of flip-chip assembly can have a long cycle time. Typically, reflows which are carried out in infrared or forced convection ovens have cycle times of 5 minutes or longer. These furnaces are usually very long ( greater than 3 m) and massive structures, occupying much space on the assembly floor. Moving parts in such furnaces are a significant source of particulate contamination.
Third, present day assembly of flip-chips is processed in chip form. The assembly process starts after the chip has been diced from the wafer. This type of production strategy causes a disconnect between the wafer fabrication and test plant (xe2x80x9cwafer fabxe2x80x9d) and the assembly and final test site because the dicing of the wafer must occur outside the clean room environment of a wafer fab. In addition, there are substantial costs in shipping valuable wafers worldwide. After packaging is completed in the assembly sites, the devices must undergo final testing before they can be shipped to the customer. A need thus exists for a packaging method that provides for wafer-scale assembly of integrated circuits, preferably in the clean room facility of the wafer fab itself.
In accordance with the present invention, there is provided first a multitude of semiconductor devices for application in board or systems assembly and multi-chip modules in digital signal processing, microprocessor, memory and other commercial and military products requiring flexibility, high reliability and cost-effectiveness; secondly a process aiming a low-cost manufacturability, far reduced number of process steps and easy rework, all of which offer an economic advantage over the prior art and also avoid the generation of chemical waste byproducts which would require costly disposition; and thirdly, an apparatus for aligning, reflowing and attaching solder balls to semiconductor devices at the wafer level. The process used is low in particulate generation, a clean process which may be incorporated into or placed adjacent to a wafer fabrication facility. The method provides for a wafer bumping interconnection for integrated circuit devices which is compatible with the wafer processing equipment already in use in the wafer fabs.
The invention also provides a method and apparatus for attaching a secondary interconnections onto solder balls of semiconductor devices at the wafer level. The use of interposers is known to provide increased reliability and mechanical performance when using solder ball flip-chip technology. The embodiment described herein provides a methodology for producing packaged devices at the wafer level and leaving only the dicing and symbolization steps to complete the integral circuits. Because the interposers provide additional mechanical performance, higher performance units can be packaged at the wafer fab.
It is an object of the present invention to provide a low-cost method and system for packaging chip-size devices at the wafer level.
Another object of the present invention is to provide a method for clean processing compatible with the clean room facilities and equipment installed in the wafer fabs.
Another object of the present invention is to simplify assembly and testing requirements by eliminating the need to ship wafers to assembly/test sites for packaging and rather complete the products in the wafer fabs.
Another object of the present invention is to shorten the manufacturing cycle time for packaging and use computer control extensively for assuring process control.
Another object of the present invention is to simplify the assembly of semiconductor wafers by reducing it to two process steps, repeated several times sequentially: Aligning and heating.
Another object of the present invention is to minimize the cost of capital investment and the movement of parts and product in the equipment.
Another object of the present invention is to provide a technology for assembling integrated circuits while maximizing the number of minimizing the feature size of inputs/outputs.
Another object of the present invention is to develop a flexible, efficient, economical, mass producible technology for dense packaging of semiconductor chips.
These objects have been achieved by a mass production process using a combination of thin film carriers, plastic interposers, fine-geometry coupling members, computer-controlled rapid processing equipment, and a variety of solder combinations and melting temperature. Various modifications have been employed for the assembly of silicon wafers as well as connective substrates.